Flash memory is nonvolatile memory capable of electrically writing or erasing data, and enables the rewriting of data within a limited number of times. Information stored in flash memory is not deleted even if power is turned off, and flash memory has been widely used as storage devices for portable electronic devices, such as digital cameras, Personal Digital Assistants (PDAs), MP3 players, or mobile phones, because of its advantages, such as low-power consumption, a high operating speed, and excellent durability. Recently, flash memory has been utilized in various areas, such as a Solid State Disk (SSD) or turbo memory. Below, the structure of flash memory will be described with reference to Korean Unexamined Patent Publication No. 2011-0016320.
FIG. 1A is a diagram showing the typical structure of flash memory, and FIG. 1B is a diagram showing in detail a single page shown in FIG. 1A.
As shown in FIGS. 1A and 1B, flash memory can be divided into planes, each including a plurality of blocks, wherein each block is subdivided into a plurality of pages. Each page is divided into a sector that is an area in which data is stored, and a spare that is an area in which information about the data stored in the sector is stored. In this case, a host or a file system may recognize the sector area, but the spare area is an area managed by a Flash Translation Layer (FTL). In the spare area, information about the data stored in the sector is recorded, and thus information about the data stored in the corresponding sector area may be obtained if the spare area is referred to. For the sake of convenience of description, in FIGS. 1A and 1B, an example in which a single sector is included in a single page has been shown, but a single page may also include two or more sectors. Further, depending on representation, there may be a case where the sector area shown in FIGS. 1A and 1B is called a data area and where the data area and a spare area are integrally called a sector, and such a case shows a difference only in representation. Technical features desired to be actually described are same as shown in FIGS. 1A and 1B.
In flash memory, a write operation is performed on a page, and an erase operation is performed on a block. In order to write data to flash memory, a host transmits data to a flash memory storage device on a sector basis, and the storage device must allocate a specific page in which input data is to be stored. The flash memory cannot perform an in-place overwrite operation, and must perform an erase-before-write operation in order to overwrite new data to a previously used block, that is, a block to which data has been written. The number of times that the flash memory can be erased is limited to about one hundred thousand times in the case of a Single Level Cell (SLC) and to about ten thousand times in the case of a Multi-Level Cell (MLC).
In order to overcome such a limitation in the number of erasures, wear-leveling is required which prevents a specific block in flash memory from being intensively repeatedly used and from being more rapidly worn than other blocks, and which evenly distributes data to respective blocks with the result that all blocks are evenly worn. The functions of a Flash Translation Layer (FTL) that is a software layer are to maximize the performance of flash memory in consideration of those features, perform wear-leveling, and lengthen the lifespan of flash memory.
Technology related to a conventional wear-leveling technique in flash memory is disclosed in Korean Unexamined Patent Publication No. 10-2008-0033649 entitled “Flash memory system and management method thereof capable of reducing merge frequency.” In accordance with this prior art, after a merge operation has been performed, the update frequency of the corresponding data is checked, and the operation of allocating and adjusting a separate section for wear-leveling based on the update frequency is performed.
Since such conventional wear-leveling algorithms take into consideration only wear-leveling, it is assumed that the algorithms have a separate performance improvement algorithm for efficiently utilizing read, write and erase operations. However, the prior art is impossible to implement algorithms in two fields in a single FTL due to hardware constraints. In this case, the term “hardware constraints” denotes a restriction in the number of times that partial programming of flash memory is performed. The term “partial programming restriction” denotes the number of times that a single page can be accessed. For example, in a case where the total number of accesses allowed by flash memory is three, if a performance improvement algorithm consumes two accesses, the number of accesses that the wear-leveling algorithm can use is only one. Accordingly, wear-leveling algorithms requiring partial programming two or more times cannot be used.
Further, conventional wear-leveling techniques have common ground in that wear-leveling is periodically performed depending on a predetermined time or a predetermined number of operations. Such a technique causes a large variation in the performance of flash memory according to the type of write operation. In the case of a conventional wear-leveling algorithm, the number of erase operations (Erase Count Number: ECN) performed on each block is inquired about using a read operation, and thereafter an operation of replacing pieces of information of two blocks between which a predetermined number of variations occur is performed. Since this algorithm performs wear-leveling unconditionally and periodically depending on the predetermined time or the predetermined number of operations, unnecessary read and write operations occur to inquire about information even when wear-leveling is not required. For example, in a case where a predetermined time has elapsed, but only a read operation is performed, or a case where a large number of write operations have been performed, but they are evenly distributed and then an erase operation is not performed, an operation for information inquiries is performed even if wear-leveling is unnecessary.
Therefore, data management technology that is capable of considering wear-leveling while minimizing the deterioration of the performance of a flash memory device is required.
The above information disclosed in this Background section is only for enhancement of understanding of the background of the invention and therefore it may contain information that does not form the prior art that is already known in this country to a person of ordinary skill in the art.